1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of forming an alignment mark on a wafer, and a wafer comprising same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
Conventional complementary metal oxide silicon (CMOS) semiconductor devices may be referred to as “bulk” CMOS devices, because bulk CMOS devices include a substantially monocrystalline semiconducting bulk substrate in which the active and/or passive CMOS circuit elements are disposed. More recently, silicon-on-insulator (SOI) devices have been introduced that consume less power than do bulk CMOS devices, an important advantage in many applications such as battery-powered mobile telephones and battery-powered laptop computers. Also, silicon-on-insulator (SOI) devices advantageously operate at higher speeds than do bulk CMOS devices.
Silicon-on-insulator (SOI) devices may be characterized by having a thin layer of insulating dielectric material (for example, a buried oxide or nitride or other suitable insulating layer) sandwiched between a bulk semiconducting substrate and a relatively thin semiconducting layer in which the circuit elements of the device will be formed. Typically, no other layers of material are interposed between the buried dielectric layer and the bulk substrate.
In a silicon-on-insulator (SOI) device, the circuit elements of the device are formed in regions of the relatively thin, e.g., 500-1500 Å, semiconducting layer. The circuit elements are typically separated from each other by insulating dielectric regions (of field oxide, for example). The semiconducting layer may be n-doped or p-doped as appropriate with N-type or P-type conductivity dopants. A variety of semiconductor devices may be formed in the thin semiconducting layer. For example, devices such as NMOS transistors, PMOS transistors, NPN bipolar transistors, and/or PNP bipolar transistors may be formed in the thin semiconducting layer.
Silicon-on-insulator (SOI) technology offers a number of advantages relative to traditional transistor formation in a bulk silicon wafer. For example, bulk silicon transistors have their active terminals disposed adjacent the bulk silicon wafer. As a result, parasitic capacitance is present at the junction between the source/drain regions of an MOS transistor and the well or bulk silicon substrate. Other problems with bulk silicon transistors include the possibility of junction breakdown between the source/drain regions and the wafer, together with the formation of undesired parasitic bipolar transistors giving rise to device latch-up problems.
In contrast, in silicon-on-insulator (SOD technology, the transistors have active regions (for example, the source/drain and channel regions of an MOS transistor) that are formed in the thin semiconducting layer that is positioned above the underlying insulating layer. As such, formation of undesired parasitic elements in such transistors is reduced or eliminated. The silicon-on-insulator (SOI) technology also significantly reduces junction capacitance and junction leakage due to the reduced exposed junction area. This reduced parasitic capacitance leads to increased performance and higher density integrated circuits. Also, transistors formed using silicon-on-insulator technology exhibit inherent radiation hardness, better high temperature performance, higher current driving ability, and lower leakage currents.
Additionally, in some cases, silicon-on-insulator (SOI) techniques use simpler fabrication sequences as compared to circuits fabricated in bulk silicon. Silicon-on-insulator (SOI) techniques also provide reduced capacitive coupling between various circuit elements over the entire integrated circuit (IC) chip, and, in CMOS circuits, latchup is substantially reduced. Silicon-on-insulator (SOI) techniques reduce chip size and/or increase packing density, and minimum device separation is determined only by the limitations of photolithography. Moreover, silicon-on-insulator (SOI) techniques provide increased circuit speed, due in part to reductions in parasitic capacitance and chip size.
During semiconductor manufacturing processes, layers of various materials are deposited and/or spun-on and/or grown on a workpiece, such as a semiconducting wafer or die, one after the other. After many of the layers are deposited and/or spun-on and/or grown, photolithographic and etching process techniques are used to transfer patterns to the under-lying layer or layers. For the finished product to operate properly, the pattern of each layer should be precisely aligned to the patterns of the other layers on the workpiece, since misalignment of one layer with respect to a previous layer may adversely impact device performance or, in some cases, result in complete device failure. One photolithographic system commonly used is a step-and-scan pattern transfer system (using a “scanner” such as the ASM® Lithography scanner) that involves repetitively transferring a series of image patterns, often with multiple exposures for each portion of a workpiece, to cover the entire workpiece surface.
To achieve acceptable alignment, alignment marks may be formed on the workpiece. The number of alignment marks employed per wafer may vary, e.g., 2-8 per wafer. The previously formed alignment marks may then be used by the stepper tool to properly align the wafer prior to performing photolithography processes on the wafer.
In some embodiments, the alignment marks are typically a pattern of trenches formed by an etching process. The alignment marks desirably have relatively sharp edges, and depths that allows the alignment marks to be recognized by the stepper to make the alignment mark useful as an alignment tool. A typical depth of the alignment mark required by conventional steppers manufactured by ASM® Lithography is in a range of about 1000-2100 Å, although as technology continues to advance, this depth may decrease. Alignment marks used by steppers of other stepper manufacturers may need a different mark depth.
In silicon-on-insulator devices, the alignment marks are formed in the relatively thin semiconducting layer positioned above the insulating layer. However, as device dimensions continue to shrink, locating the alignment marks in the relatively thin semiconducting layer may be problematic for a variety of reasons. For example, as the thickness of the thin semi-conducting layer is reduced, there may be insufficient material to allow formation of the alignment marks in that layer. Additionally, since the layer in which the alignment marks are formed is very thin, the marks may not be as stable as would otherwise be desired. That is, even small movements in the thin semiconducting layer due to, for example, thermal variations, may introduce errors in patterning operations that are aligned by referencing alignment marks formed in such a thin layer. Moreover, during normal processing operations, the upper surface of the semiconducting layer may be exposed to processes that degrade or erode the surface of that layer. For example, the surface of the thin semiconducting layer may be subjected to a variety of heating operations that may tend to convert part of the semiconducting layer to silicon dioxide, thereby consuming part of the semiconducting layer. Additionally, the surface of the semiconducting layer may also be subjected to various cleaning operations during the course of manufacturing, e.g., a dilute acid rinse to remove unwanted native oxide. All of the processes tend to degrade the alignment mark formed in the semiconducting layer. In some cases, the degradation may adversely impact the ability to use the alignment mark in various alignment procedures.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.